This patent relates to a method for erasing data of a NAND flash memory device and more particularly to a method for erasing data of a multi-level cell (MLC) NAND flash memory device.
NAND flash memory devices are nonvolatile memory devices that are electrically programmable and erasable. NAND flash memory devices are widely used in portable electronics such as MP3 players, digital cameras, camcorders, notebook computers, PDAs, and cellular phones, a computer basic input/output system (BIOS), printers, USB drives, and the like.
When an erase operation is performed on a NAND flash memory device, a voltage of 0V is applied to a word line of a selected memory cell of the memory device and an erase voltage of about 20V is applied to a semiconductor substrate. Then, Flower-Nordheim (F-N) tunneling causes electrons, which have been stored in a floating gate, to be moved to the semiconductor substrate by a voltage difference between both ends of a tunnel oxide layer, thereby changing the threshold voltage of the cell.
Recently, a Multi-Level Cell (MLC) structure, which allows data of 2 or more bits to be selectively stored in a single memory cell, has been suggested to increase the storage capacity with a smaller chip size. The MLC structure can represent data of two bits, three bits, and even four or more bits with a single program cell threshold voltage distribution.
An operation for erasing data of an MLC flash memory device is performed according to an Incremental Step Pulse Erase (ISPE) scheme. In the ISPE scheme, one pulse with an erase voltage of, for example, about 20V is applied to each memory cell of a block and the threshold voltage of the memory cell is verified with a verify voltage of 0V to determine whether or not all the cells in the block are in the erased state. If all the cells are not in the erased state, an erased state verification method, in which a higher voltage is applied using a step voltage Vstep to again verify the erased state, is repeated until all the cells pass the erased state verification. The maximum number of loops of this procedure is previously determined.
In this conventional data erasure method, the same erase voltage and the same step voltage are applied for all blocks. That is, the same high erase voltage and the same step voltage are used without regard to the cell speeds of blocks. Thus, the conventional method cannot reduce the erasure time and also leaves the memory device easily influenced to program/erase cycling, thereby lowering the reliability of the memory device.